note: for detailed information on purchasing options, contact your local allegro field applications engineer or sales representative. allegro microsystems, inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. the information included herein is believed to be accurate and reliable. however, allegro microsystems, inc. assumes no respon- sibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use. recommended substitutions: 8-bit serial-input dmos power driver a6b595 for existing customer transition, and for new customers or new appli- cations, contact allegro sales. date of status change: may 3, 2010 deadline for receipt of last time buy orders: october 29, 2010 this part is in production but has been determined to be last time buy. this classification indicates that the product is obsolete and notice has been given. sale of this device is currently restricted to existing customer applications. the device should not be purchased for new design applications because of obsolescence in the near future. samples are no longer available. last time buy
description the a6b595 combines an 8-bit cmos shift register and accompanying data latches, control circuitry, and dmos power driver outputs. power driver applications include relays, solenoids, and other medium-current or high-voltage peripheral power loads. the serial-data input, cmos shift register and latches allow direct interfacing with microprocessor-based systems. serial- data input rates are over 5 mhz. use with ttl may require appropriate pull-up resistors to ensure an input logic high. a cmos serial-data output enables cascade connections in applications requiring additional drive lines. similar devices with reduced r ds(on) are available as the a6595. the a6b595 dmos open-drain outputs are capable of sinking up to 500 ma. all of the output drivers are disabled (the dmos sink drivers turned off) by the output enable input high. copper lead frames, reduced supply current requirements, and low on-state resistance allow both devices to sink 150 ma from all outputs continuously, to ambient temperatures over 85c. the a6b595 is furnished in a 20-pin dual in-line plastic package and a 20-pin wide-body, small-outline plastic package (soicw) with gull-wing leads. the pb (lead) free versions (suffix -t) have 100% matte tin leadframe plating. 26185.122g features and benefits ? 50 v minimum output clamp voltage ? 150 ma output current (all outputs simultaneously) ? 5 ? typical r ds(on) ? low power consumption ? replacement for tpic6b595n and tpic6b595dw 8-bit serial-input dmos power driver packages: functional block diagram not to scale a6b595 18-pin dip (a package) 20-pin soicw (lw package) grounds (terminals 10, 11, and 19) must be connected together externally.
8-bit serial-input dmos power driver a6b595 2 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com absolute maximum ratings characteristic symbol notes rating units logic supply voltage v dd 7v output voltage v o 50 v input voltage range v i ?0.3 to 7.0 v output drain current i o continuous; each output, all outputs on 150 ma i om peak; pulse duration 100 s, duty cycle 2% 500 ma single-pulse avalanche energy e as 30 mj operating ambient temperature t a range k ?40 to 85 oc maximum junction temperature t j (max) 150 oc storage temperature t stg ?65 to 150 oc caution: these cmos devices have input static protection (class 3) but are still susceptible to damage if exposed to extremely high static electrical charges. selection guide part number package packing a6b595ka-t 18-pin dip 18 pieces per tube a6b595klwtr-t 20-pin soicw 1000 pieces per reel thermal characteristics characteristic symbol test conditions* value units package thermal resistance r ja package a, 1-layer pcb with copper limited to solder pads 65 oc/w package lw, 1-layer pcb with copper limited to solder pads 90 oc/w *additional thermal information available on the allegro website 50 75 100 125 150 2.5 0.5 0 allowable package power dissipation in watts ambient temperature in o c 2.0 1.5 1.0 25 dwg. gs-004a suffix 'a', r = 65 o c/w q ja suffix 'lw ', r = 9 0 o c/w q ja
8-bit serial-input dmos power driver a6b595 3 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com note that the a package (dip) and the lw package (soic) are electrically identical and share a common terminal number assignment. pin-out diagram ground 1 2 3 8 9 13 14 15 16 17 19 4 5 6 7 12 18 20 serial data out serial data in logic supply v dd strobe ground clock clk st out 7 out 6 out 5 dwg. pp-029-12 out 0 out 1 out 2 out 3 out 4 10 11 no connection no connection nc nc output enable oe register clear ground clr terminal descriptions terminal no. terminal name function 1 nc no internal connection. 2 logic supply (v dd ) the logic supply voltage (typically 5 v). 3 serial data in serial-data input to the shift-register. 4-7 out 0-3 current-sinking, open-drain dmos output terminals. 8 clear when (active) low, the registers are cleared (set low). 9 output enable when (active) low, the output drivers are enabled; when high, all output drivers are turned off (blanked). 10 ground reference terminal for output voltage measurements (out 0-3 ). 11 ground reference terminal for output voltage measurements (out 0-7 ). 12 strobe data strobe input terminal; shift register data is latched on rising edge. 13 clock clock input terminal for data shift on rising edge. 14-17 out 4-7 current-sinking, open-drain dmos output terminals. 18 serial data out cmos serial-data output to the following shift register. 19 ground reference terminal for input voltage measurements. 20 nc no internal connection. note ? grounds (terminals 10, 11, and 19) must be connected together externally.
8-bit serial-input dmos power driver a6b595 4 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com truth table shift register contents serial latch contents output contents data clock data output input input i 0 i 1 i 2 ... i 6 i 7 output strobe i 0 i 1 i 2 ... i 6 i 7 enable i 0 i 1 i 2 ? i 6 i 7 h h r 0 r 1 ? r 5 r 6 r 6 l l r 0 r 1 ? r 5 r 6 r 6 x r 0 r 1 r 2 ? r 6 r 7 r 7 x x x ? x x x ? r 0 r 1 r 2 ? r 6 r 7 p 0 p 1 p 2 ? p 6 p 7 p 7 p 0 p 1 p 2 ? p 6 p 7 l p 0 p 1 p 2 ? p 6 p 7 x x x ? x x h h h h ? h h l = low logic level h = high logic level x = irrelevant p = present state r = previous state serial data out logic inputs dmos power driver output recommended operating conditions over operating temperature range logic supply voltage range, v dd ................ 4.5 v to 5.5 v high-level input voltage, v ih ............................ 0.85v dd low-level input voltage, v il ................................. 0.15v dd
8-bit serial-input dmos power driver a6b595 5 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com limits characteristic symbol test conditions min. typ. max. units output breakdown v (br)dsx i o = 1 ma 50 ? ? v voltage off-state output i dsx v o = 40 v, v dd = 5.5 v ? 0.1 5.0 a current v o = 40 v, v dd = 5.5 v, t a = 125c ? 0.15 8.0 a static drain-source r ds(on) i o = 100 ma, v dd = 4.5 v ? 4.2 5.7 on-state resistance i o = 100 ma, v dd = 4.5 v, t a = 125c ? 6.8 9.5 i o = 350 ma, v dd = 4.5 v (see note) ? 5.5 8.0 nominal output i on v ds(on) = 0.5 v, t a = 85c ? 90 ? ma current logic input current i ih v i = v dd = 5.5 v ? ? 1.0 a i il v i = 0, v dd = 5.5 v ? ? -1.0 a serial-data v oh i oh = -20 a, v dd = 4.5 v 4.4 4.49 ? v output voltage i oh = -4 ma, v dd = 4.5 v 4.0 4.2 ? v v ol i ol = 20 a, v dd = 4.5 v ? 0.005 0.1 v i ol = 4 ma, v dd = 4.5 v ? 0.3 0.5 v prop. delay time t plh i o = 100 ma, c l = 30 pf ? 150 ? ns t phl i o = 100 ma, c l = 30 pf ? 90 ? ns output rise time t r i o = 100 ma, c l = 30 pf ? 200 ? ns output fall time t f i o = 100 ma, c l = 30 pf ? 200 ? ns supply current i dd(off) v dd = 5.5 v, outputs off ? 20 100 a i dd(on) v dd = 5.5 v, outputs on ? 150 300 a i dd(fclk) f clk = 5 mhz, c l = 30 pf, outputs off ? 0.4 5.0 ma typical data is at v dd = 5 v and is for design information only. note ? pulse test, duration 100 s, duty cycle 2%. electrical characteristics at t a = +25c, v dd = 5 v, t ir = t if 10 ns (unless otherwise speci ed).
8-bit serial-input dmos power driver a6b595 6 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com timing requirements and specifications (logic levels are v dd and ground) a. data active time before clock pulse (data set-up time), t su(d) .......................................... 20 ns b. data active time after clock pulse (data hold time), t h(d) .............................................. 20 ns c. clock pulse width, t w(clk) ............................................. 40 ns d. time between clock activation and strobe, t su(st) ....................................................... 50 ns e. strobe pulse width, t w(st) ............................................... 50 ns f. output enable pulse width, t w(oe) ................................ 4.5 s note ? timing is representative of a 12.5 mhz clock. higher speeds are attainable. serial data present at the input is transferred to the shift reg- ister on the rising edge of the clock input pulse. on succeed- ing clock pulses, the registers shift data information towards the serial data output. information present at any register is transferred to the respective latch on the rising edge of the strobe input pulse (serial-to-parallel conversion). when the output enable input is high, the output source drivers are disabled (off). the information stored in the latches is not affected by the output enable input. with the output enable input low, the outputs are controlled by the state of their respective latches.
8-bit serial-input dmos power driver a6b595 7 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com test circuits single-pulse avalanche energy test circuit and waveforms e as = i as x v (br)dsx x t av /2 logic symbol
8-bit serial-input dmos power driver a6b595 8 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com package a, 18-pin dip package lw, 20-pin soicw 5.33 max 0.46 0.12 22.86 0.51 6.35 +0.76 ?0.25 3.30 +0.51 ?0.38 10.92 +0.38 ?0.25 1.52 +0.25 ?0.38 7.62 2.54 0.25 +0.10 ?0.05 c seating plane 2 1 18 a dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown a terminal #1 mark area all dimensions nominal, not for tooling use (reference jedec ms-001 ac) dimensions in inches 2 1 20 2 1 20 a 2.65 max c seating plane c 0.10 20x a terminal #1 mark area gauge plane seating plane b 2.25 0.65 9.50 1.27 pcb layout reference view for reference only dimensions in millimeters (reference jedec ms-013 ac) dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown b reference pad layout (reference ipc soic127p1030x265-20m) all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances 1.27 0.25 0.20 0.10 0.41 0.10 12.800.20 10.300.33 7.500.10 4 4 0.27 +0.07 ?0.06 0.84 +0.44 ?0.43
8-bit serial-input dmos power driver a6b595 9 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com copyright ?1999-2009, allegro microsystems, inc. the products described here are manufactured under one or more u.s. patents or u.s. patents pending. allegro microsystems, inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro?s products are not to be used in life support devices or systems, if a failure of an allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. for the latest version of this document, visit our website: www.allegromicro.com
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